1. Field of the Invention
The present invention generally relates to a carrier recovery circuit and a lock detection circuit and, more particularly, to a carrier recovery circuit provided in a phase shift keying (PSK) demodulating circuit for recovering a carrier from an input signal in which a plurality of PSK modulated signals using different M-ary encoding techniques are mixed, and to a lock detection circuit for detecting a locked state of a negative feedback loop of the carrier recovery circuit, based on the input signal. In this specification, M of the M-ary encoding will be referred to as an M value.
2. Description of the Related Art
FIG. 10 is a block diagram showing a construction of a carrier recovery circuit according to the related art. Referring to FIG. 10, the carrier recovery circuit comprises a multiplier 101 for recovering a carrier by multiplying a complex signal (I, Q), produced by subjecting a PSK modulated signal to quadrature demultiplexing, by a signal from a numerically-controlled oscillator (NCO) 111. Numeral 102 indicates a phase detection unit for detecting a phase error of the recovered carrier. Numeral 104 indicates a frequency detection unit for detecting a frequency error of the recovered carrier. Numeral 106 indicates a multiplier for multiplying the phase error by a predetermined pgain. Numeral 107 indicates a multiplier for multiplying the frequency error by a predetermined fgain. Numeral 108 indicates an adder for adding a result of computation submitted by the multiplier 106 and a result of computation submitted by the multiplier 107. Numeral 109 indicates a loop filter coupled to an output of the adder 108. Numeral 110 indicates an accumulator for accumulating outputs from the loop filter 109. Numeral 111 indicates a numerically-controlled oscillator for generating a signal at a frequency commensurate with an output of the accumulator 110.
A description will now be given of the operation of the carrier recovering circuit according to the related art.
The carrier recovering circuit according to the related art includes a negative feedback loop. When an input signal is a PSK modulated signal having a single M value, the carrier is continuously recovered in a locked state.
The multiplier 101 multiplies the complex signals (I, Q) by the signal from the numerically-controlled oscillator 111. The signal produced as a result of multiplication is output as the recovered carrier. The recovered carrier is then subject to phase error detection by the phase detection unit 102. FIG. 11 is a graph showing the characteristics of the phase detection unit 102 exhibited when detecting a phase error from a BPSK modulated signal. The frequency detection unit 104 detects the frequency error. The multiplier 106 multiplies the phase error by the predetermined pgain. The multiplier 107 multiplies the frequency error by-the predetermined fgain. The adder 108 adds the result of computation submitted by the multiplier 106 and the result of computation submitted by the multiplier 107.
The loop filter 109, with predetermined filtering characteristics, subjects the output of the adder 108 to low-pass filtering. The accumulator 110 accumulates the outputs of the loop filter 109. The NCO 111 generates a signal having a frequency commensurate with the output of the accumulator 110 so as to output the generated signal to the multiplier 101.
With this construction, negative feedback is imposed so that the phase error and the frequency error are reduced. Once the locked state is achieved, the carrier is recovered in a stable manner.
Accordingly, the related-art recovery circuit is capable of properly recovering the carrier provided that the M value of the modulated PSK signal is constant.
However, the related-art recovery faces difficulties when the input signal contains a mixture of PSK modulated signals having different M values. For example, when the PSK modulated signals including the BPSK modulated signal, the QPSK modulated signal and the 8PSK modulated signal, which are used in the broadcast system (BS) in Japan, are mixed, convergence to a locked state and stable recovery of the carrier are difficult to achieve.
Once approach to remedy this drawback is to construct the carrier recovery circuit of FIG. 10 to adapt to a PSK modulated signal with a predetermined single M value (for example, a BPSK modulated signal). Associated with this, the input PSK modulated signal is monitored to determine whether the circuit is adapted for the M value of the input PSK modulated signal. As shown in FIG. 12, only when the M value of the input signal is the prescribed M value, pgain and fgain are set to predetermined non-zero values. Only the complex signal for the PSK modulated signal having the prescribed M value is selected so that the carrier is recovered. FIG. 12 illustrates how pgain and fgain are set to values corresponding to the M value of the input signal.
An example where M=2, 4, 8, that is, where the BPSK modulated signal, the QPSK modulated signal and the 8PSK modulated signal are involved, will now be discussed. FIG. 13A is a constellation diagram of the BPSK modulated signal in an I-Q plane; FIG. 13B is a constellation diagram of the QPSK modulated signal in an I-Q plane; and FIG. 13C is a constellation diagram of the 8PSK modulated signal in an I-Q plane. Each of the circles in FIGS. 13A–13C indicates a signal point of the respective modulated signal. Given that the power of phase error of the BPSK modulated signal, QPSK modulated signal and 8PSK modulated signal is indicated by EB, EQ and E8, respectively and the phase error that produces the minimum power is indicated by θeq, B, θeq, Q and θeq, 8, respectively, the phase errors θeq, B, θeq, Q and θeq, 8 are given by respective ones of the following equations.
                                          E            B                    =                                                                      1                  2                                ⁢                                  θ                  2                                            +                                                1                  2                                ⁢                                  θ                  2                                                      =                          θ              2                                      ⁢                                  ⁢                                                            ⅆ                                  E                  8                                                            ⅆ                θ                                      |            θ                    =                                    θ                              eq                ,                B                                      =                                          0                ⇒                                  θ                                      eq                    ,                    B                                                              =              0                                                          (        1        )                                                      E            Q                    =                                                                      1                  2                                ⁢                                                      (                                          Δ                      -                      θ                                        )                                    2                                            +                                                1                  2                                ⁢                                                      (                                          Δ                      +                      θ                                        )                                    2                                                      =                                          Δ                2                            +                              θ                2                                                    ⁢                                  ⁢                                                            ⅆ                                  E                  Q                                                            ⅆ                θ                                      |            θ                    =                                    θ                              eq                ,                Q                                      =                                          0                ⇒                                  θ                                      eq                    ,                    Q                                                              =              0                                                          (        2        )                                                      E            8                    =                                                                      1                  4                                ⁢                                                      (                                                                  Δ                        ′                                            +                      θ                                        )                                    2                                            +                                                1                  4                                ⁢                                                      (                                                                  3                        ⁢                                                  Δ                          ′                                                                    +                      θ                                        )                                    2                                            +                                                1                  4                                ⁢                                                      (                                                                  3                        ⁢                                                  Δ                          ′                                                                    -                      θ                                        )                                    2                                            +                                                1                  4                                ⁢                                                      (                                                                  Δ                        ′                                            +                      θ                                        )                                    2                                                      =                                          5                ⁢                                  Δ                  2                                            +                              θ                2                                                    ⁢                                  ⁢                                                            ⅆ                                  E                  8                                                            ⅆ                θ                                      |            θ                    =                                    θ                              eq                ,                8                                      =                                          0                ⇒                                  θ                                      eq                    ,                    8                                                              =              0                                                          (        3        )            where Δ=π/4 and Δ7=π/8.
FIG. 14 is a block diagram showing a configuration of a lock detection circuit according to the related art. Referring to FIG. 14, the lock detection circuit comprises a BPSK area detection unit 141 for detecting whether the position, in the I-Q plane, of the complex signal (I, Q) subject to quadrature demultiplexing is found in a reference range described later. The lock detection also comprises an adder 142, a delay circuit 143 and a comparator 144.
A description will now be given of the operation according to the related art. FIG. 15 shows reference areas for the BPSK modulated signal in the I-Q plane.
The BPSK area detection unit 141 segments the I-Q plane into four angular sectors, so that an area between −π/4 and +π/4 and an area between 3π/4 and 5π/4 being used as reference areas. That is, angular sectors between (4i−1)π/(2M) and (4i+1)π/(2M), where i is a positive number between 0 and M-1, are used as reference areas. In the case of BPSK modulated signal, M=2 so that the angular sector (i=0) between −π/4 and +π/4and the angular sector (i=1) between 3π/4 and 5π/4 being are used as reference areas.
The BPSK area detection unit 141 determines by computation the position of input complex signal in the I-Q plane so as to determine whether the position is found in the reference area. If the position is found in the reference area, the BPSK area detection unit 141 outputs +1. Otherwise, it outputs −1.
The adder 142 and the delay circuit 143 accumulates the values provided by the BPSK area detection unit 141 so as to provide the accumulated value to the comparator 144. The comparator 144 determines whether the accumulated value reaches a predetermined threshold value. If it is determined that the accumulated value reaches the predetermined threshold value, the comparator 144 outputs a signal indicating that a locked state has set in.
More specifically, when demodulated signals located within the reference area (signals with a relatively higher probability of being a BPSK modulated signal) occur more frequently than the other demodulated signals, it is determined in the carrier recovery circuit adapted for the BPSK modulated signal according to the related art that the locked state has set in.
For example, given that the position of the complex signal subject to multiplication by the multiplier 101 in the carrier recovery circuit is rotated in a counterclockwise direction in the I-Q plane, the position moves away from a closest signal point (phase=0) while the position is 0−π/2 phase shifted with respect to the signal point. Therefore, the phase error has a negative value and decreases in this range. The frequency error has a negative value. When the position of the complex signal is π/2−π phase shifted with respect to the signal point, the position moves closer to the signal position (phase=π). The phase error has a positive value and decreases. The frequency error has a negative value.
When the negative feedback loop in the carrier recovery circuit is in a pull-in state, the position of the complex signal subject to multiplication by the multiplier 101 may be found in an area outside the reference area (non-reference area). When the negative feedback loop in the carrier recovery circuit is in a locked state, the position of the complex signal subject to multiplication by the multiplier 101 is more likely found in the reference area. FIG. 16 shows an example of how the output value of the delay circuit 143 in the lock detection circuit according to the related art varies. As shown in FIG. 16, in a pull-in state, the output value of the delay circuit 143 (that is, the accumulated value produced by the outputs of the BPSK area detection unit 141) decreases with oscillation. When the locked state sets in, the output value of the delay circuit 143 increases.
With the above-described construction of the carrier recovery circuit according to the related art, a carrier recovery from a PSK modulated signal having a predetermined M value is possible. However, no measures are provided to recover a carrier for a mixture of a plurality of PSK modulated signals having different M values, using a simple circuit configuration.
One approach would be to embed data indicating the M value in a modulated signal so that the M value is known when demodulating the signal based on the data so that the carrier recovery circuit adapted for the M value is used to recover a carrier. This requires provisions for processes and circuits for embedding the data in a modulating stage, and provisions for processes and circuits for detecting the data and switching between carrier recovery circuits in a demodulating stage. Therefore, difficulties with reduction in circuit scale and processing time remain.